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SRI International Sr. FPGA Design Engineer in Princeton, New Jersey

Sr. FPGA Design Engineer
Job LocationsUS-MI-Ann Arbor | US-CO-Boulder | US-NJ-Princeton | US-CA-Menlo Park
ID2024-5923CategoryEngineeringPosition TypeFull-TimeWorker TypeHybrid
Overview

SRI International's Advanced Technology & Systems Division has an immediate opportunity for a Sr. FPGA Design Engineer in our Applied Physics Laboratory. You will have the ability to work a hybrid work schedule (some days in the office, some days from home office), with flexible hours. Work Locations are the following: Boulder, CO, Princeton, NJ, Ann Arbor, MI or Menlo Park, CA.

The Lab conducts R&D in radar, communications, electronic warfare, Positioning, Navigation, and Timing (PNT), Intelligence, Surveillance and Reconnaissance (ISR), quantum sensing, and machine learning. We have a commitment to the deeply intellectual work required for our applied research and creative solutions. We foster a commitment to quality that our small, nimble teams execute. Smaller teams mean more responsibility and close-knit relationships. We value collaboration where solving hard problems is part of the fun.

ATSD is known for work in intelligence, surveillance, and reconnaissance. We're at the leading edge of human-machine interaction, sensing, and other applied technologies that are turning data into usable knowledge.

Responsibilities

With experience in Field Programmable Gate Array (FPGA) design as it relates to digital signal processing (DSP), radar, communications and EW systems, you will be expected to contribute on current programs and quickly grow into a task leader.

    Have success taking a project/program from white board to detail during intake meeting
  • Take ideas from the initial meeting and modify based on inputs
  • Leave initial meeting with an architecture plan
  • Mentor junior staff into independent roles
  • Write and implement Verilog code with extremely low latency
  • Exercise judgement in selecting methods, techniques and evaluation for solutions
  • Resolve complex issues in creative and effective ways
Qualifications
  • BS with 8+ years; or MS with at least 6 years'; or PhD with at least 3 years' related experience
  • U.S. Citizenship is required, with an active Secret clearance
  • Applied FPGA design engineering
  • Relevant applications include real-time radar or communication systems, or similar applications with strict latency requirements
  • FPGA design experience including concept development, code development, simulation, and verification on hardware
  • Digital and embedded system architecture design, including high-level and detailed low-level design
  • DSP understanding and application
  • Experience or familiarity of the following techniques: matched filtering, range-Doppler, SAR, monopulse, and backprojection imaging techniques
  • Familiarity with Software Defined Radios (SDRs) and Graphic Processing Units (GPUs) for the purpose of managing and processing radar data
  • Radar and communication system design and development
  • System engineering including integration, testing and evaluation of prototype systems
  • Verilog, SystemVerilog, VHDL, or other suitable hardware description languages
  • Willingness to contribute to white papers and technical proposals and ability to brief US government customers
  • Capable of working in a team environment and managing multiple priorities

Desired Qualifications and Skills:

  • An active TS clearance, ideally related to past experience with classified RF work
  • Active SCI, and recent SAP experience
  • Advanced radar and RF communication waveform design and usage
  • Microprocessor embedded software development
  • C/C++, Python, Matlab coding expertise
  • Exceptional communication and presentation skills, especially when communicating complex ideas to a diverse audience

SRI is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class.

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